Computing devices sometimes implement a non-uniform memory access (NUMA) scheme using two or more NUMA nodes. NUMA nodes often include, at least, one or more processors and some amount of memory (e.g., random access memory (RAM), cache, etc.). The time necessary for a given processor to access data (i.e., latency) from within the same NUMA node that the processor is in may be lower than the time necessary to access data from memory in other NUMA nodes of a computing device. Attempts to reduce the time needed to access data in computing devices implementing NUMA (e.g., by making variables and/or data structures NUMA-aware) may lead to increased cache cross-coherency traffic and/or an increase in the amount of memory used to store representations of the data.